1. Field of the Invention
The present embodiments relate to a plasma display panel, and more particularly, to a plasma display panel capable of reducing the defect rate of a dielectric layer.
2. Description of the Related Art
Plasma display panels (PDPs), which are being recently spotlighted as a replacement for conventional cathode ray tube (CRT), are display devices that display images by applying a discharge voltage to a discharge gas between two substrates with a plurality of electrodes formed on the substrates to generate ultraviolet (UV) rays, and exciting a phosphor material having a predetermined pattern with the UV rays.
Typical alternating current (AC) PDPs include a front substrate, a rear substrate, a plurality of discharge electrodes, a dielectric layer in which the discharge electrodes are buried, barrier ribs that define discharge cells, and a frit with which the front substrate and the rear substrate are sealed together.
FIG. 1 is a schematic plan view of a rear substrate of a conventional AC PDP. For convenience of explanation, illustration of barrier ribs is omitted.
As illustrated in FIG. 1, a dielectric layer 11 formed on a rear substrate 10 extends to over the edges of the rear substrate 10. Corners 11a of the dielectric layer 11 are buried in a frit 12.
In other words, the frit 12 is located on the edges of the rear substrate 10 and a front substrate (not shown) in order to seal the rear substrate 10 and the front substrate. Since the corners 11a of the dielectric layer 11 are angled toward the outside of the rear substrate 10, they are located at positions where the frit 12 is coated. Hence, the corners 11a are buried in the frit 12.
After the coating of the frit 12 and an assembly of the rear substrate 10 and the front substrate, a baking process is required to attach the rear substrate 10 and the front substrate together. Since the baking process is performed at high temperature, deformation of the rear substrate 10, the front substrate, the dielectric layer 11, and the frit 12 usually occur.
However, in most cases, the dielectric layer 11 and the frit 12 have different thermal expansion coefficients. Hence, different degrees of thermal expansions of the dielectric layer 11 and the frit 12 attached to each other during the baking process create many thermal stresses.
When many thermal stresses are generated as described above, the dielectric layer 11 can be peeled, cracked, or broken during the baking process. This increases the defect rate of the dielectric layer 11. Although the dielectric layer 11 does not directly fail during the baking, the dielectric layer 11 becomes weak against external vibrations and impacts due to residual stresses.